1. Field of the Invention
The present invention relates to an IC device applicable to electronic equipment, such as, a television receiver, VTR, tape recorder, or the like, having a digitally controlled internal circuit and, more particularly, is directed to an IC device suitable as a CPU or a microprocessor having a communication line.
2. Description of the Prior Art
Most video and audio equipment, such as, television receivers, VTRs, tape recorders, or the like, which have a digital circuit employ an inner bus system, for example, as shown in FIG. 1, in which a main CPU 1 and a plurality of IC devices 2.sub.1,2.sub.2, . . . , and 2.sub.n are connected to each other through a bus line 3, and the IC devices 2.sub.1,2.sub.2, . . . , 2.sub.n control circuits 4.sub.1,4.sub.2, . . . , and 4.sub.m. The IC devices 2.sub.1 to 2.sub.n fetch predetermined data from data supplied by CPU 1, D/A-convert the fetched data, and use the resulting analog signals to control circuits 4.sub.1 to 4.sub.m. At the same time, IC devices 2.sub.1 to 2.sub.n receive and A/D-convert operation voltages from circuits 4.sub.1 to 4.sub.m, and supply the obtained digital signals to CPU 1. As a result, IC devices 2.sub.1 to 2.sub.n function as a slave CPU.
Further, in FIG. 1, a ROM 5 stores set values of the operation voltage of circuits 4.sub.1 to 4.sub.m. In normal operation, a set value is read from ROM 5 by CPU 1 and the readout data is supplied to IC devices 2 to 2.sub.n through bus line 3, so that circuits 4.sub.1 and 4.sub.m are controlled to perform predetermined operations while a display unit 6 provides a suitable display, for example, an indication that such operations are being performed. The circuits 4.sub.1 to 4.sub.m are also externally controlled by manual actuation of a keyboard 7, or by a remote control system, through CPU 1.
As shown on FIG. 2, four-line type buses have been usually used as the bus line 3 in an inner bus system of the type shown on FIG. 1. However, recently, two-line type buses have been coming into use for that purpose, as shown on FIG. 3.
More particularly, in the four-line type bus arrangement shown on FIG. 2, CPU 1 and IC devices 2.sub.1,2.sub.2, . . . 2.sub.n are connected in common through three lines 8.sub.1,8.sub.2, and 8.sub.3. Chip select terminals CS.sub.1,CS.sub.2, . . . CS.sub.n of CPU 1 and chip select terminals CS.sub.11,CS.sub.12,CS.sub.1n of the IC devices 2.sub.1,2.sub.2, . . . 2.sub.n, are connected to each other through lines 9.sub.1,9.sub.2, . . . 9.sub.n, respectively. When CPU 1 selectively communicates with IC device 2.sub.1, it supplies a chip select signal of "L" level from terminal CS.sub.1 to the respective terminal CS.sub.11, and a signal of "H" level from terminals CS.sub.2, . . . CS.sub.n to the terminals CS.sub.12, . . . CS.sub.1n of the other IC devices 2.sub.2, . . . 2.sub.n. The line 8.sub.1 transmits data from CPU 1 to IC devices 2.sub. 1,2.sub.2, . . . 2.sub.n, the line 8.sub.2 transmits data from the IC devices 2.sub.1,2.sub.2, . . . 2.sub.n to CPU 1, and line 8.sub.3 transmits a clock pulse from CPU 1 to IC devices 2.sub.1,2.sub.2, . . . 2.sub.n. Shift registers (not shown) are provided in the IC devices 2.sub.1,2.sub.2, . . . 2.sub.n. When a chip select signal is supplied to the IC devices 2.sub.1,2.sub.2, . . . 2.sub.n for selecting one of those IC devices, data supplied from CPU 1 through the line 8.sub.1 is fetched by the shift registers of the selected IC device. The shift registers also supply data stored therein to the CPU 1 through the line 8.sub.2.
Referring in detail to FIG. 3, it will be seen that when the two-line type bus line is used in the arrangement of FIG. 1, CPU 1' and IC devices 2'.sub.1,2'.sub.2, . . . 2'.sub.n are connected in common through two lines 10.sub.1 and 10.sub.2. In this case, line 10.sub.1 is used for alternately transmitting and receiving serial data between CPU 1' and IC devices 2'.sub.1,2'.sub.2, . . . 2'.sub.n, and line 10.sub.2 is used for transmitting a clock pulse. Specific addresses are assigned to IC devices 2'.sub.1,2'.sub.2, . . . 2'.sub.n, which selectively fetch the data when they detect their respective addresses in the data supplied from CPU 1'. A communication system using the two-line type bus line is disclosed in detail in Japanese Patent Disclosure No. 57-106262.
The two-line type bus line is advantageous in that it reduces the number of wires required, as compared with the four-line type bus line. On the other hand, the four-line type bus line can transmit a large amount of data within a short period of time, that is, the two-line type bus line has a relatively slower transmission speed. Accordingly, the four-line type bus line has been used for equipment, such as, a VTR, which requires complex control functions, while the two-line type bus line has been used in those applications where the controlled equipment, for example, a television receiver, involves relatively simpler control functions. In connection with the foregoing, it is to be noted that, in a VTR, various predetermined circuits, such as a timer circuit, a display circuit, a drive mechanism, a servo circuit, and the like, must be monitored sequentially and constantly within a one-field period of a video signal. It has been found that such monitoring and consequent control cannot be performed within a one-field period when using a two-line type bus line by reason of the relatively slower transmission speed of that type of bus line.
Referring now to FIGS. 4A-4C showing the data format of the signals transmitted by the two-line type bus line of FIG. 3, it will be seen that line 10.sub.1 transmits serial data D (FIG. 4B) and the other line 10.sub.2 transmits a clock CL (FIG. 4C). The data D is shown on FIG. 4A to comprise a 1-bit start signal, a 7-bit address signal for designating the address assigned to one of the IC devices 2'.sub.1,2'.sub.2, . . . 2'.sub.n, a 1-bit R/W signal for determining whether to supply data to the designated IC device or to fetch data from the designated IC device, a 1-bit acknowledge or ACK signal which is sent to the CPU 1' when it is confirmed that an IC device is designated and that such IC device has received data, an 8-bit data signal representing a control level or the like, n 9-bit data signals, and a 1-bit stop signal.
It will be appreciated that the IC devices 2.sub.1,2.sub.2, . . . 2.sub.n used in connection with the four-line type bus line in FIG. 2 and the IC devices 2'.sub.1,2'.sub.2, . . . 2'.sub.n used in connection with the two-line type bus line in FIG. 3 have different arrangements and thus are not generally compatible with each other. However, in order to realize the above-described advantages of the both types of bus lines, it is sometimes desirable to use an IC device for the two-line type bus lines in a system using the four-line type bus lines. Further, it may be desirable to combine a VTR using a four-line type bus line and a television receiver using a two-line type bus line in a system which is controlled by a main CPU common to both the VTR and television receiver.